1. Field of the Invention
The invention relates to methods for the fabrication of dielectric separation layers between conductor layers in microelectronics fabrications. More particularly, the invention relates to methods for fabrication of relatively low dielectric constant dielectric layers between conductor layers in microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by dielectric layers.
As the level of integration of microelectronics devices has increased and the dimensions of microelectronics devices have decreased, the spacing between adjacent conductor layers carrying current has correspondingly decreased.
Similarly, in accord with the desire for higher performance, speeds of electrical circuit operation have increased greatly. Such higher speeds typically require minimization of parasitic capacitance in conductor layers adjacent to signal carrying layers to decrease time required for charging of stray capacitances, and capacitive coupling between adjacent signal conductor lines minimized in order to attenuate cross-talk and distortion due to excessive capacitive coupling. For these reasons, it has become common to employ low relative dielectric constant dielectric layers formed interposed between patterned microelectronics conductor layers within microelectronics fabrications. As is understood by persons skilled in the art, the relative dielectric constant of a dielectric material is the ratio between the dielectric constant of the material and the dielectric constant of empty space, which is taken as unity; thus the relative dielectric constant will be numerically equal to that ratio, and will be referred to as the dielectric constant of the material.
Of the methods and materials which may be employed for forming low dielectric constant dielectric layers interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications, methods which provide dielectric layers which in turn define vacuum evacuated or gas filled (such as but not limited to air filled) voids interposed between the patterns of patterned microelectronics conductor layers are particularly desirable within the art of microelectronics fabrication. Such methods are desirable since vacuum evacuated or gas filled voids typically yield within a microelectronics fabrication a dielectric layer possessing in the pertinent locations interposed between a series of patterns which comprises a patterned microelectronics conductor layer a dielectric constant approaching the theoretical lower limit of 1.0. For comparison purposes, conventional silicon containing dielectric layers formed of silicon containing dielectric materials such as but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials typically exhibit homogeneous dielectric constants within a range of from about 4.0 to about 9.0. Similarly, alternative low dielectric constant dielectric layers formed from low dielectric constant dielectric materials such as but not limited to organic polymer spin-on-polymer (SOP) dielectric materials (such as but not limited to polyimide organic polymer spin-on-polymer (SOP) dielectric materials, poly (arylene ether) organic polymer spin-on-polymer (SOP) dielectric materials and fluorinated poly (arylene ether)organic polymer spin-on-polymer (SOP) dielectric materials), amorphous carbon dielectric materials and silsesquioxane spin-on-glass (SOG) dielectric materials (such as but not limited to hydrogen silsesquioxane (HSQ) spin-on-glass (SOG) dielectric materials, carbon bonded hydrocarbon (MSQ) silsesquioxane spin-on-glass (SOG) dielectric materials and carbon bonded fluorocarbon silsesquioxane (FSQ) spin-on-glass (SOG) dielectric materials) typically exhibit somewhat lower homogeneous dielectric constants in a range of from about 2.5 to about 3.3.
It is therefore towards the goal of forming within microelectronics fabrications low dielectric constant dielectric layers which define, at least in part, vacuum evacuated or gas filled voids interposed between the patterns of patterned conductor layers upon which are formed those low dielectric constant dielectric layers, that the present invention is more generally directed.
Various methods and associated microelectronics structures have been disclosed within the art of microelectronics fabrication for forming upon patterned microelectronics conductor layers within microelectronics fabrications microelectronics dielectric layers which at least in part define vacuum evacuated or gas filled voids interposed between the patterns which comprise patterned conductor layers within microelectronics fabrications.
For example, Graven et al., in U.S. Pat. No. 5,641,712, disclose a method for forming a dielectric layer which define a series of voids between conducting lines thus reducing capacitance between the conducting lines. The voids are formed when a silane oxide layer is deposited over the lines to form a nearly closed trench-like gap in the oxide between the lines which is subsequently closed off at the top and sealed by resputtering the top surface of the oxide.
Further, Havemann et al., in U.S. Pat. No. 5,461,003, disclose another method which employs a dielectric layer for forming voids between metal layer leads of a semiconductor device. The voids are formed by depositing first a disposable solid layer between the metal layer leads, covering said leads and disposable layer with a porous dielectric layer, and removing the disposable layer through the porous covering dielectric layer.
Still further, Stoltz et al., in U.S. Pat. No. 5,407,860, disclose a method for defining a series of voids interposed between a series of patterns which comprises a patterned conductor layer within an integrated circuit microelectronics fabrication when forming upon the patterned conductor layer within the integrated circuit microelectronics fabrication a dielectric layer. The method employs a non-wetting material formed upon at least the sidewalls of the series of patterns which comprises the patterned conductor layer but not completely occupying the spaces between the series of patterns which comprises the patterned conductor layer nor upon the top surfaces of the series of patterns which comprises the patterned conductor layer. Thus, when a dielectric layer is subsequently formed upon the patterned conductor layer having the non-wetting material selectively formed upon portions of its patterns there is formed a series of voids beneath the dielectric layer, where the series of voids is formed interposed between the series of patterns which comprises the patterned conductor layer.
Finally, Sliwa et al., in U.S. Pat. No. 5,192,715, disclose a method for producing voids selectively at the sidewalls of aluminum lines within a microelectronics fabrication coated with tungsten. The method employs a selective deposition and dissolution of a sacrificial tungsten layer upon the sidewalls of the aluminum lines.
Desirable in the art of microelectronics fabrication are additional methods and materials which may be employed for forming a dielectric layer over a patterned microelectronics layer within a microelectronics fabrication, such that a series of vacuum evacuated or gas filled voids is defined interposed between a series of patterns which comprises the patterned microelectronics layer when forming the dielectric layer over the patterned microelectronics layer. More particularly desirable in the art of integrated circuit microelectronics fabrication are additional methods and materials which may be employed for forming a dielectric layer over a patterned conductor layer within an integrated circuit microelectronics fabrication, such that a series of vacuum evacuated or gas filled voids is formed interposed between a series of patterns which comprises the patterned conductor layer when forming the dielectric layer over the patterned conductor layer.
It is towards the foregoing goals that the present invention is both generally and more specifically directed.